This invention relates to memory cells of the type used in random access memory devices implemented in largescale-integrated semiconductor circuits.
Complex integrated circuits made for use in calculators or other data processing systems, or computer main frame memory arrays, employ MOS memory cells which have been of several types. Static cells or flip-flop circuits have been generally avoided, because of the excessive space needed for each cell. Dynamic cells using a capacitor as the storage mechanism are widely used. A common example is the "three transistor cell" type as shown in U.S. Pat. No. 3,585,613 or in U.S. Pat. No. 3,893,088, issued July 1, 1975, assigned to Texas Instruments Incorporated. The three transistor cell has found great utility; one disadvantage, however, is that it must be refreshed periodically. The voltage on the storage capacitance decays after a certain period, and so the data stored must be read out and written back in to make sure that data are not lost. The need for refresh imposes requirements for programming, sense circuitry and feed back amplifier circuitry. One transistor cells of the type set forth in U.S. Pat. No. 3,909,631 issued Sept. 30, 1975 and assigned to Texas Instruments Incorporated, have the same requirement for refresh, circuitry for this purpose is shown in U.S. Pat. No. 3,737,879. In attempts to eliminate the need for refresh in random access memory or RAM cells, various types of "self-refreshing" cells have been proposed. An example of such cells is shown in Digest of Technical Papers, 1972 IEEE International Solid State Circuits Conference, pages 14-15, by T. R. Walther and M. R. McCoy. The so-called invisible refresh cell provides an apparently static (refresh without addressing) operation in a dynamic-sized cell. Another example is described in copending U.S. patent application Ser. No. 454,349, filed Mar. 25, 1974 by Marion E. Cavanaugh, now U.S. Pat. No. 3,876,993, issued Apr. 8, 1975 assigned to Texas Instruments Incorporated. However, there are objections to these prior cells. Generally, when it is attempted to reduce the size of the cell to a minimum so that a large number of cells can be fabricated on a single chip along with other logic and memory functions, and also to specify the device for operation over a wide range of supply and clock voltage levels and a wide temperature range, then in some cases a stored ground level will not be properly reinforced.